Typical integrated memory circuits include arrays of memory cells arranged in rows and columns. In most memory arrays, several redundant rows and columns are provided, which substitute for defective memory cells. When testing circuitry that tests the array identifies a defective memory cell, rather than treating the entire array as defective, a redundant row or column is substituted for the row or column having the defective memory cell (i.e., for the "defective" row or column). This substitution is performed by assigning the address of the defective row or column to tie redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make substitution of the redundant row or column substantially transparent to a system employing the memory circuit, the memory circuit includes ail address detection circuit. The address detection circuit monitors the row and column addresses received from the system employing the memory circuit. When the address detection circuit receives the address of a defective row or column, it enables the redundant row or column instead.
One type of address detection circuit is a fuse-bank address detection circuit. Fuse-bank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address word. The sense lines are programmed by blowing fuses in the sense lines in a pattern corresponding to the address word of the defective row or column. The programmed addresses are then detected by first applying a test voltage across the bank of sense lines. Then, bits of an external address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of external address bits, the sense lines all block current and the voltage across the bank remains high. Otherwise, at least one sense line conducts and the voltage falls. A high voltage thus indicates the programmed address matches the external address. A low voltage indicates a different external address has been applied.
Typically, the fuses are blown by cutting the fuse conductors with a laser to remove the conductive paths through the fuses. One problem with such an approach is that laser cutting of the fuses is time consuming, difficult, and imprecise. As a consequence, the cost and reliability of memory devices employing fuse bank circuits can be less than satisfactory.
To eliminate the cost, difficulty, and expense of laser cutting, memory devices have recently been developed that employ antifuses in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be "blown" by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct and unblown antifuses do not conduct.
FIG. 1 shows a typical prior art antifuse circuit 46 from an antifuse bank in greater detail. As noted above, each redundant row and column is addressable by a single programmed address. Therefore, each antifuse bank must correspond to one redundant row or column. If a given memory cell is addressable by an eight bit address word, then eight of such antifuse circuits 46 will together form an antifuse bank. Typically, each antifuse bank will contain an array of antifuses for a redundant row, and an array of antifuses for a redundant column. The antifuse circuit 46 of FIG. 1 shows only one of several antifuse circuits within an antifuse bank that store addresses for both a redundant row and a redundant column. Each of the antifuse circuits 46 in an antifuse bank therefore is identical except for the blown or unblown state of row and column antifuses 48R and 48C, respectively, in each. Consequently, the following description applies equally to all of the antifuse circuits 46 in the antifuse bank.
The antifuse circuit 46 receives three principal input signals: an initiation signal T(RAS), a device enable signal DVC2E, and a reset signal RST. The T(RAS) signal is a delayed version of the row address select signal RAS, which is a common on-chip signal in many memory devices. Like the row address select signal RAS, the T(RAS) signal is a low-true signal. The device enable signal DVC2E is a conventional, on-chip signal at approximately half of the supply voltage V.sub.CC, while the reset signal RST is an externally generated signal that resets the antifuse circuit 46 to the appropriate initial conditions.
In addition to the input signals T(RAS), DVC2E and RST, the antifuse circuit 46 also receives a switchable signal CGND at a switchable node 50. During normal operation, the switchable signal CGND is set to ground to provide a reference for checking the state of the antifuses 48R and 48C. For blowing the antifuses 48R, 48C, the switchable signal CGND is a high voltage, typically greater than 10 volts.
The antifuse circuit 46 includes four principal portions, a row output latch 52R, a row latch control circuit 53, a column output latch 52C and a column latch control circuit 53C. In general, elements in FIG. 1 having a "R" designation following the reference numeral indicates a circuit element for the row portion of the antifuse bank, while a "C" following the reference numeral corresponds to the column portion. While only the row output latch 52R and row latch control circuit 53R are described, such description applies equally to the operation of the column output latch 52C and the column latch control circuit 53C.
The row latch 52R is formed from three PMOS transistors 56R, 58R, 60R and an inverter 62R. The first and second transistors 56R, 58R are coupled in parallel with their sources coupled to the supply voltage V.sub.CC and their drains coupled at a node 64R. The gate of the first transistor 56R is controlled by the T(RAS) signal and the gate of the second transistor 58R is controlled by the output of the inverter 62R, which is also inverted again by an inverter 63R to become the output signal FR of the antifuse circuit 46. In this configuration, if either the T(RAS) signal or the output of the inverter 62R is low, the node 64R will be coupled to the supply voltage V.sub.CC through the first or second transistor 56R, 58R, respectively. The third transistor's gate is grounded so that the third transistor 60R is always on. Therefore, the third transistor 60R couples the node 64R to the inverter input. The third transistor 60R has a high channel length-to-width ratio so that it has a high channel resistance, typically about 300 k.OMEGA. or more. The third transistor 60R thus forms a constant, high resistance path between the node 64R and the input to the inverter 62R.
Ignoring the effect of the latch control section 53R, operation of the latch 52R is controlled by the T(RAS) signal. Initially, the output signal FR from the row latch 52R is low. Consequently, the gate of the second transistor 58R will be high such that the second transistor 58R is off. Initially, the T(RAS) signal is also high, so the first transistor 56R is off, isolating the node 64R from the supply voltage V.sub.CC. The voltage at the node 64R will be low, because the latch control section 53R forms a path for current to bleed to ground, as described below. The third transistor 60R couples the voltage at node 64R to the inverter 62R so that the input voltage of the inverter is low. The inverter 62R thus continues to supply a high voltage to the gate of the second transistor 58R, keeping the second transistor off and maintaining the initial conditions.
After the initial conditions are established, the T(RAS) signal goes low, turning on the first transistor 56R. In response, supply voltage V.sub.CC pulls the voltage at node 64R high, through the first transistor 56R. The third transistor 60R transmits the high voltage at node 64R to the input of the inverter 62R. In response, the inverters 62R, 63R set the output signal FR high, thereby turning on the second transistor 58R. At this point, both the first and second transistors 56R, 58R are on.
Later (after address detection is complete), the T(RAS) signal returns high, turning off the first transistor 56R- However, the voltage at node 64R remains high, because the second transistor 58R is latched on through the inverter 62R since the input voltage to the inverter 62R is high and the inverter 62R keeps the second transistor 58R on. The output signal FR thus remains high, even after the T(RAS) signal returns high.
The row latch control circuit 53R is formed from a control transistor 66R and three current legs, all joined at a control node 68R. During normal operation, the control transistor 66R is turned on by the device enable signal DVC2E to couple the control node 68R to the input of the inverter 62R. The inverter's input voltage can therefore be controlled by a control voltage at the control node 68R.
The control voltage is controlled by one or more of the three current legs. The first or reset leg establishes the initial conditions of the row latch 52R. The reset leg is formed from an NMOS reset transistor 76R coupled between the control node 68R and ground. The reset signal RST drives the gate of the reset transistor 76R, such that when the reset signal RST is high, the reset transistor connects the control node 68R to ground. When the reset leg pulls the inverter input low, it forces the output signal FR to go low. This turns off the second transistor 58R. The T(RAS) signal is also high, because the initial conditions are established when address detection is inactive. Therefore, the first transistor 56R is also off. With both the first and second transistors 56R, 58R off, the voltage at the node 64R is pulled low. The row latch 52R is thus forced into the stable state described above with the output signal FR low, and the row latch remains set even after the reset signal RST is removed.
The second or reference leg forms a self-decoupling current path for blowing the antifuse 48R. The reference leg includes a pass NMOS transistor 78R and a decoupling NMOS transistor 80, serially coupled between the control node 68 and ground. The pass transistor 78R is controlled by a row address signal RAx which represents a bit of an address. The address signal RAx is active when the T(RAS) signal is active, such that the pass transistor 78R conducts when RAx is high (inactive) and blocks current when RAx is low (active). If the address signal RAx is low, the pass transistor 78R deactivates the reference leg so that it does not affect the response of the row latch 52R.
The decoupling transistor 80 is controlled by an antifuse programming signal FAMx that represents one bit of an address to be programmed into the bank of antifuses. The decoupling transistor 80 (and the pass transistor 76R) couple the control node 68R to ground only when the particular bit for the programmed address is high (i.e., FAMx is high). When the control node 68R is coupled to ground through the decoupling transistor 80, a high voltage can be applied as the CGND signal to the switchable node 50 during programming to program the antifuse 48R.
The third or antifuse sense leg includes an NMOS drop transistor 82R serially connected with the antifuse 48R between the control node 68R and the switchable node 50. The gate of the drop transistor 82R is directly coupled to the supply voltage V.sub.CC (or a higher voltage V.sub.CCP) so that the drop transistor is always on. The drop transistor 82R therefore acts as a resistive element between the control node 68R and the antifuse 48R. Also, the drop transistor 82R limits the maximum voltage applied to the control node 68 during programming of the antifuse 48R to the supply voltage V.sub.CC minus the threshold voltage V.sub.T of the drop transistor. Consequently, the drop transistor 82R limits the drain-to-gate voltages of the transistors 76R, 78R and the source-to-gate voltage of the control transistor 66R to limit breakdown of the gate oxide.
When the antifuse 48R is unblown, the antifuse 48 forms an open circuit, and thus does not affect the voltage at node 68R and does not affect the latch 52. When the antifuse 48R is blown, however, the antifuse 48 has an impedance of approximately 5 k.OMEGA.. The blown antifuse 48R and drop transistor 82R form a conductive path between the control node 68R and the switchable node 50, allowing the switchable signal CGND to affect the voltage at control node. During address detection, the switchable signal CGND is coupled to ground, pulling down the voltage at the control node 68R, which causes the input of the inverter 62R to go low, tripping the latch 52R. The output signal FR then goes low, indicating that the antifuse 48R is blown. The output signal FR remains low even when the T(RAS) signal goes high, because the control transistor 66R, the drop transistor 82R and the blown antifuse 48R draw sufficient current to overpower the third transistor 60R. Thus, when the antifuse 48R is blown, the output signal FR goes low and stays low.
As noted above, for an eight bit address word, eight of such antifuse circuits 46 are required to address a redundant row and a redundant column. If a memory device employs eight redundant rows and eight redundant columns, sixty-four of such antifuse circuits 46 (for eight antifuse banks) are required. Sixty-four of such antifuse circuits 46 adds to the complexity of the memory device, which can increase the probability of defects, and possibly increase the number of manufacturing/processing steps.
Additionally, sixty-four of such antifuse circuits 46 consume substrate area on a die onto which the memory device is formed. Furthermore, certain transistors in each of the antifuse circuits 46 must be able to withstand high voltages during programming of the antifuses (e.g, transistors 60R, 60C, 78R, 78C, 80, 82R, and 82C). These high voltage transistors also require increased substrate area over typical transistors. Semiconductor circuit designers always desire to reduce substrate area to allow additional functionality to be added to a given device, allow for improved manufacturing tolerances, etc. Therefore, it would be desirable to reduce the number of antifuse circuits 46.
An additional shortcoming of the prior antifuse circuits relates to the lengthy time required to latch a signal in the row/column latch 52R, 52C. As noted above, the third transistor 60R (and 60C) has a high channel resistance. Since the row latch 52R unnecessarily has an inherent RC time constant required to latch a signal therein, an increased resistance caused by the transistor 60R therefore increases the RC time constant. As a result, the row latch 52R (and the column latch 52C) is slower to latch the output signal FR therein, than if the transistor 60R had a low channel resistance. As the speed of memory devices increases, there is increasing need for faster circuitry employed therein, including antifuse bank circuitry, which must be accessed during each read/write operation. The third transistor 60R provides a high resistance path from V.sub.CC to ground if the antifuse 48R (or 48C) is blown (i.e., the path through the transistors 56R, 60R, 66R, and 82R). Without such a high resistance path, high current flow through this path could damage the antifuse circuit 46. Consequently, the high resistance element cannot be removed from the path to speed up the response time of the antifuse circuit 46.